Serial Wire Ring - 1711

Internal buses do not leave the ECU. They connect the integrated circuits (ICs) on the board to each other. These buses transmit data from input circuits (e.g. analog-digital converters) to the controller or data to activate output stages from the controller to the output stages. Since these buses are only used inside one ECU, voltage levels, signal type (symmetrical or asymmetrical), impedances, and bit rate can be configured differently, depending on the requirement.

 

Features
The Serial Wire Ring (SWR) is the modern successor to the Serial Peripheral Interface (SPI). Its advantages are the
higher bit rate and only two pins per user as opposed to four pins (CLK, MOSI, MISO, CS) in the SPI. As the price for
these advantages the SWR requires a more complex logic in the transmitter and in the receiver, particularly to recover the
clock signal from the data stream. Only two pins per user provide for small housings and less wiring on the board. This is made possible by a ring topology as pictured in Figure 1. This has the additional benefit of the master being able to read back all data and thereby discover transmission errors. This is an important feature for safety-related systems.

Topology
The ring consists exclusively of point-to-point connections, providing for high data rates. Each connection transmits the data from precisely one source to precisely one destination in only one direction (Figure 1):
Master → Slave 0 → Slave 1 → ... → Slave N − 1 → Master.
The ring contains one master and 1 to 16 slaves. Since all are similarly connected to each other in the ring, it is optionally
possible for alternately a different module in the ring to assume the role of master. Each user in the ring forwards the received signal with two clocks delay to the next user. The level of the signal is thereby conditioned. Even small time fluctuations of the signal edges (jitter) are reduced with the aid of clock data recovery (CDR). In this way, different signal levels can be realized within a ring.

 

4b/5b encoding of data
Clock and data are jointly transmitted via a line in the ring. The receiver extracts the data and the clock from this signal by
means of clock data recovery (CDR). To enable the clock to be recovered even in the event of many consecutive “0” or “1”, a special 4b/5b encoding as depicted in Table 1 is used: Every fourth bit is inverted and then sent again. With this encoding there is a change from “0” to “1” or vice versa after five clocks at the latest. The drawback is that five bits have to be sent over the bus to transmit four data bits.

Transmission is performed according to the following scheme: The lowest-value bit is always transmitted first and the highest-value bit is transmitted last.

 

Clock rate
The clock rate is not tied down to specific values, but can be chosen to suit the required data rate and latency. The lower
limit is 1 MHz, the upper limit is determined by the slowest user and the line routing.
 Signal transmission from precisely one source to precisely one destination facilitates higher data rates than with a
branched line such that the Serial Wire Ring can be operated at 10 to 100 times the clock frequency of the Serial Periph-
eral Interface. The demand for higher speed mentioned at the start is thus fulfilled.

 

Data transmission
The interframe symbol and the data frame or the interrupt frame are transmitted al-ternately by the master on the data line (2).

AddressingAddressing
The slaves are addressed via an address field in the data frame. Each slave receives its address automatically via its
position in the ring during the initialization of the ring. The first slave receives the address 0, the last of N slaves receives the address N − 1.

 

Data frame
The data frame serves to transmit user data between master and slave. With the same data frame the master can also
send data to several slaves and receive data from several slaves. At the same time it is possible to transmit data from slave to slave, but only in the circulation direction of the ring.
The master continuously sends frames through the ring. If no data have to be transmitted, it sends “zero frames”.

Interrupt frame
Interrupt frames are regularly sent by the master within a fixed time interval. Each slave which has reserved one or more bits in the interrupt frame can use such a bit to trigger a specific reaction in the master. This reaction usually consists of delivering or collecting data.

 

Interframe symbol
To enable each user in the ring to detect the start of a frame, the interframe symbol (IFS, Figure 2) is situated between
two frames. It is 14 bits long and differs from each possible 14-bit sequence of the 4b/5b-encoded signals in at least two bits. This ensures that a 1-bit error does not lead to the appearance of an interframe symbol in the regular 4b/5b data stream. Each user in the ring compares the last 14 received bits with the interframe symbol. If they match, the user begins to evaluate the frames that now follow. In the event of errors, it aborts the evaluation and waits for the next interframe symbol.

Data frame
Identifier

Figure 3 shows a data frame in detail. The leading 1 identifies the frame as a data frame. A 01 would indicate a zero frame and a 0010 an interrupt frame.

Data frame counter

The data frame counter (DFC) is a 2-bit counter which the master increments before it sends a new data frame. This is important in the event of a transmission error that the master notices when reading back. It then repeats the data frame with the same DFC. If the error has occurred on the way from the master to the slave, the slave now receives the data frame for the first time and evaluates it. If the error has occurred on the way from the slave to the master, the slave now receives the data frame for the second time, detects this by the unchanged DFC, and now does not evaluate it for a second time.

Slave address
The slave address SLADR addresses the slave. The primary addresses 0 to N − 1 address precisely one slave at the
corresponding position in the ring. Higher values up to 31 are used for group addresses. While the ring is being initial-
ized, the master can instruct one or more slaves to execute a particular operation automatically if a certain group address
appears, for example to output bits 12 to 16 to five output stages. In this way, the master can carry out complex data transfers later without further instructions and thus very quickly simply by using the associated group address. The participating slaves then “know” what is to be done.

Parity bit
PAR is a parity bit for the first eight bits. It is sufficient in order to detect 100 % of all single-bit errors. Double-bit errors are detected by the master when reading back and lead to a bus reset. Therefore they do not have to be detected by PAR. This procedure is possible because double- and multiple-bit errors are very rare.

Data field
The actual data field comes after PAR. It can contain any number of bits from 1 to 256.

 

Primary address
In the event of a primary address, i.e. if the master only addresses this slave, the slave processes the entire data field and if necessary places an answer at the end of the data field. In the process it overwrite part of the data field so that the master can no longer read back its message to the slave. If this is not permitted for security reasons or if the slave’s answer is already longer than the master’s message, the master must configure the data field bigger and for example append zeros. The slave then overwrites only this areas and no old data are lost. However, this gives rise to a larger data field, i.e. a longer transmission time.

 

Group address
In the event of a group address, each slave can, according to its previously learned instructions, evaluate and change any bits of the data field.

Cyclic redundancy check
The concluding 10-bit CRC (cyclic redundancy check) is supported by slaves for which this is useful. There are also simple slaves which do not support the CRC in order to save costs. The CRC is required to back up critical data on their way from the slave to the master. Because, while the master can detect all the other transmission errors when reading back, this is not possible with the answer data from a slave. The slaves which belong to a group address must all jointly use the CRC, or not.

Filler bitsFiller bits
Because of the 4b/5b encoding the data frame must always contain a multiple of four bits. It may therefore be necessary
finally to append up to three more zeros in order to reach the next multiple higher of four

 

Sequence control in the master
As transmission rates increase, it is becoming increasing more difficult for a CPU to make available the transmission data in good time via a simple send and receive register and to collect the received data fast enough. Therefore the SWR master automatically accesses the memory. This memory also contains one or more chained lists with instructions as to which transactions the master is to execute (queues).
 Once activated, the master works through a queue instruction by instruction down to the last instruction or to an in-
struction with a set stop bit. A software command, an external trigger (e.g. by a timer) or the already described prompt by
a slave by means of interrupt frame can reactivate the queue.

 The end of a queue can refer back to the start and thereby form a closed loop. In this way, the same instructions can be executed again and again. If an instruction is disrupted by a transmission error, the master repeats it automatically. Each instruction contains a priority. This does not play a role as long as only one queue is active. However, as soon as several queues are active and therefore several instructions are due to be executed at the same time, the master selects the instruction with the highest priority